A circuit disclosed in Non-patent Document 1 reduces the effect of noise on a signal by amplifying a signal from a column using a high-gain amplifier connected to the column. An amplifier of a circuit disclosed in Non-patent Document 2 has two amplification factors of one and eight to satisfy both a reduction in noise and a wide dynamic range. A circuit disclosed in Non-patent Document 3 provides low-noise signal readout. In this readout, the peripheral circuits of an image sensor include a two-step noise-canceling circuit including a high-gain amplifier.
Patent Document 1 discloses an A/D converter array and an image sensor. The A/D converter array and the image sensor generate a signal of the difference between the signal level and the reset level and amplify this difference signal by n times using three capacitors. Patent Document 2 discloses an image sensor having a digital noise-canceling function. Such an image sensor generates digital values through A/D conversion on the signal level and the reset level of an image array and then determines the difference therebetween, without a noise canceling column circuit for.    Non-patent Document 1: A. Krymski, N. Khaliullin, H Krymski, N. Khaliullin, H. Rhodes, “A 2e noise 1.3 Megapixel CMOS sensor,” Proc. IEEE workshop CCD and Advanced Image Sensors, Elmau, Germany.    Non-patent Document 2: M. Sakakibara, S. Kawahito, D. Handoko, N. Nakamura, H. Satoh, M. Higashi, K. Mabuchi, H. Sumi, “A high-sensitivity CMOS image sensor with gain-adaptive column amplifiers,” IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1147-1156, 2005.    Non-patent Document 3: N. Kawai, S. Kawahito, “Noise analysis of high-gain low-noise column readout circuits for CMOS image sensors”, IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 185-194 (2004).    Patent Document 1: Japanese Unexamined Patent Application Publication No. 2005-136540    Patent Document 2: Japanese Unexamined Patent Application Publication No. 2006-25189